DSPIC30F2011-20I/SO【PDF 9/66 页】IC DSPIC MCU/DSP 12K 18SOIC

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Sheet目录3862

5页 6页 7页 8页 [9页]10页 11页 12页 13页

2010

Micr

och

echn

ology

Inc.

DS70102K-p

age

dsPIC30F

Flash

Programming

ecification

TABLE 5-10:

dsPIC30F CONFIGURATION REGISTERS (FOR dsPIC30F2011/2012, dsPIC30F3010/3011/3012/3013/3014, dsPIC30F4013 AND

dsPIC30F5015/5016)

Address

Name

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0xF80000

FOSC

FCKSM<1:0>

—

FOS<2:0>

—

FPR<4:0>

0xF80002

FWDT

FWDTEN

—

FWPSA<1:0>

FWPSB<3:0>

0xF80004

FBORPOR

MCLREN

—

PWMPIN(1)

HPOL(1)

LPOL(1)

BOREN

—

BORV<1:0>

—

FPWRT<1:0>

0xF80006

FBS

—

Reserved(2)

—

Reserved(2)

—

Reserved(2)

0xF80008

FSS

—

Reserved(2)

—

Reserved(2)

—

Reserved(2)

0xF8000A

FGS

—

Reserved(3)

GCP

GWRP

0xF8000C

FICD

BKBUG

COE

—

ICS<1:0>

Note

On the 2011, 2012, 3012, 3013, 3014 and 4013, these bits are reserved (read as ‘1’ and must be programmed as ‘1’).

Reserved bits read as ‘1’ and must be programmed as ‘1’.

3: The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).

TABLE 5-11:

dsPIC30F CONFIGURATION REGISTERS (FOR dsPIC30F6010A/6011A/6012A/6013A/6014A AND dsPIC30F6015)

Address

Name

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0xF80000

FOSC

FCKSM<1:0>

—

FOS<2:0>

—

FPR<4:0>

0xF80002

FWDT

FWDTEN

—

FWPSA<1:0>

FWPSB<3:0>

0xF80004

FBORPOR

MCLREN

—

PWMPIN(1)

HPOL(1)

LPOL(1)

BOREN

—

BORV<1:0>

—

FPWRT<1:0>

0xF80006

FBS

—

RBS<1:0>

—

EBS

—

BSS<2:0>

0xF80008

FSS

—

RSS<1:0>

—

ESS<1:0>

—

SSS<2:0>

0xF8000A

FGS

—

GSS<1:0>

GWRP

0xF8000C

FICD

BKBUG

COE

—

ICS<1:0>

Note

On the 6011A, 6012A, 6013A and 6014A, these bits are reserved (read as ‘1’ and must be programmed as ‘1’).

BWRP

SWRP

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